The D.Module2.C6657 is based on the Texas Instruments Keystone dual-core processor TMS320C6657. The Keystone multicore DSPs are characterized by huge computational power and fast serial interfaces. In the D.Module2 family it can be used independently or in conjunction with vertically stacking data acquisition and FPGA modules.

Key Features

  • TMS320C6657 dual-core DSP
  • Gbit Ethernet, PCIe
  • 512 Mbytes RAM
  • high throughput parallel and serial peripheral interfaces
  • I2C, SPI, UART, USB, and GPIO
  • stand-alone operation
D.Module2.C6657 DSP Module


The D.Module2.C6657 is perfectly suitable for radar applications, nondestructive material inspection, machine vision and software defined radio (SDR). An optional FPGA for data preprocessing is easily interfaced through Serial Rapid IO (SRIO), PCI express (PCIe) or via the fast Universal Parallel Port (uPP). Gigabit Ethernet enables network integration for control, remote maintenance and data streaming.

DSPTMS320C6657dual-core 1.25 GHz fixed- and floating-point, up to 40 GMAC / 20 GFLOP per core
MemoryDSP-internal32K bytes data cache, 32K bytes program cache per core, 1M byte direct mapped or level-2 cache per core, 1M byte shared RAM
 DDR3512M bytes, DDR3-1333, 32-bit wide
 Flash8M bytes NOR (SPI interface, sector architecture), 64M bytes SLC NAND
Ethernet1000Base-T, 100Base-Tx, 10Base-Tonboard PHY and magnetics, 1000Base-Fx Fiber support with external transceiver
USB1.112 Mbit/s
UARTRS232, RS422, RS485transmit and receive Fifo, DMA support, RS232: max 460,8K baud, automatic hardware flow-control, RS422/485: max. 20M baud
PCIe2 lanesGen. 2, up to 5 GBaud per lane
SRIO2 lanesSRIO 2.1, up to 5 GBaud per lane
SPI1max. 50 Mbps, master and slave mode
I2C1max. 400 kbps, 7 and 10 bit addressing modes, master and slave mode
McBSP2independent receivers and transmitters, max. 50 Mbps throughput
Timer82 x 32/64 bit with external I/O, 6 x 32/64 bit with internal clocking
GPIO16bit-wise programmable, input or output (in UPP Mode only 8 GPIO signals are available)
External Bus InterfaceEMIF or UPP
EMIFasynchronous transfers, 16 bit data bus, 20 address lines, 2 pre-decoded chip selects, configurable timing
UPPsynchronous mode, 2 ports, 16- or 8-bit wide, max. clock: 75MHz
  *) EMIF and UPP are exclusive modes and cannot be used simultaneously
Real-Time Clock1provision for external buffer power supply
System Supervisor watchdog, voltage and temperature, optional fan control and tacho supervisor
Emulation Interface JTAG
I/O LevelLVTTL / LVCMOSall signals except ETH, PCIe and SRIO: high level min. 2V, max. 3.5V, low level min. -0.2V, max. 0.8V, output drive: external bus interface:± 12 mA, all others ± 4 mA
Power Supply3.3Vsingle supply, 2A typ., 3A peak
FirmwareD.Module2.BIOSbootloader, board initialization, board configuration, flash memory programming, UART and USB I/O
 Setup Utilityprogram and data file uploads to the flash memory via USB or UART
 Config Fileuser- configurable text file with program and initialization parameters
Temperature Range 0 – 55°C, 0 – 70°C with forced cooling
ConnectorsBUS1, BUS2, COM, EXPMolex 71436-2164
 PCIe / SRIOMolex 46556-1145
 JTAG14-pin, 2.54mm pitch
Mechanics 86.8 x 58.4 mm, overall height including heatsink: 33mm
ROHS compliant
D.Module2.C6657standard module
D.Module2.C6657iIndustrial temperature range module -40..+85°C (forced cooling) -40..+65°C (heatsink)
DS.TCPIP-DM6657Ethernet Development Support Package for D.Module2.C6657
DK.C6657C6657 development kit including D.Module2.C6657, XDS200 JTAG in-circuit emulator, D2.Base.P base board, power supply, RS232 and USB cable, support software, and user’s guide.
DK.C6657-FMCC6657 and FPGA development kit including D.Module2.C6657, D.Module2.6SLX45T, XDS200 JTAG in-circuit emulator, D2.Base-FMC base board, power supply, USB cable, DSP support software, FPGA interface examples in VHDL, and user’s guides.


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