The D.Module2.C6557 is a TMS320C6657 DSP module offering a versatile embedded DSP single board solution for developers - requiring a more powerful integrated floating point processor capability as well as extensive communications and I/O capabilities.
Primarily intended for OEM developers looking to reduce time to market while lowering total cost, It can be used as a stand-alone system, or as a mezzanine daughtercard embedded within a larger system or board design.
The D.Module2.C6657 incorporates a powerful dual-core floating point TMS320C6657 Keystone DSP Processor, capable of performing up to 40GMACs / 20GFLOPs per core, combined with 512MBytes of DDR3 RAM, FLASH ROM, and a host of communication and I/O interfaces: I2C; USB; a UART with RS232 and RS422 line drivers; 1000Base-T Ethernet with on-board magnetics or external fiber transceivers; PCIe and a SRIO link operating up to 5 GBaud, and 16 bit-programmable I/O ports.
High-speed data converters can be directly interfaced to the parallel peripheral interface, which supports data rates up to 120M bytes/sec. For higher speed devices, an FPGA board can be inserted in the signal processing chain to provide data buffering and pre-processing. The FPGA can be cost-efficiently interfaced via the parallel peripheral interface or - for the most demanding applications - via SRIO (serial Rapid-I/O).
The D.Module2.C6657 operates from a single 3.3V supply. The parallel interface, I2C, SPI, McASP, and GPIO ports are 3.3V LVTTL compatible to facilitate system integration. The 8MByte of non-volatile Flash Memory stores program code, data sets, and configuration settings. The Flash can be conveniently (re-)programmed in-field via the resident D.Module2.BIOS functions.
A base board D.Module2.Base is available for prototyping and evaluation.
The modular, self-stacking concept facilitates building complete signal processing systems and allows for the addition of FPGA boards into the signal processing chain, between the data acquisition front end and the DSP. All on-board peripherals are comfortably initialized and programmed via D.Module2.BIOS functions.
In situations where additional functionality is required, developers can extend the capabilities of the D.Module2.C6657, using optionally available data acquisition and I/O modules, or with their own application-specific hardware.
|DSP||TMS320C6657||Dual-core 1.25 GHz fixed- and floating-point, up to 40GMAC/20GFLOP per core|
|Memory||DSP-internal||32K bytes data cache, 32K bytes program cache per core
1M byte direct mapped or level-2 cache per core
1M byte shared RAM
|DDR3 RAM||512M bytes, DDR3-1333, 32-bit wide|
|Flash||8M bytes, SPI interface, sector architecture
optional NAND Flash
|Ethernet||1000Base-T / 100Base-Tx / 10Base-T||MAC integrated in TMS320C6657, onboard PHY and magnetics
1000Base-Fx Fiber support (external transceivers)
|UART||1||RS232 line interface, max. 460.8K baud, automatic hardware flow-control
or RS422/485 line interface, max. 20M baud
transmit and receive FIFOs, DMA support
|External Bus Interface||EMIF or UPP||EMIF-Mode: 16 bit data bus, 20 address lines,
2 pre-decoded chip selects, configurable timing
UPP-Mode: synchronous Fifo interface, two ports
16- or 8-bit wide, max. clock: 75MHz
|32/64 bit, internal or external clock
32/64 bit, internal clocking
|Serial Ports||2 McBSP||independent receiver and transmitters, up to 50Mbps throughput|
(8 if external bus interface is configured to UPP mode)
|I²C||1||up to 400kbps, 7 and 10 bit addressing modes, master and slave mode|
|SPI||1||up to 50Mbps, master and slave mode|
|PCIe||2 lanes||Gen. 2, up to 5 GBaud per lane|
|SRIO||2 lanes||SRIO 2.1, up to 5 GBaud per lane|
|System Supervisor||board temperature, supply voltage
optional fan control with tacho input
|Real Time Clock (RTC)||1||provision for external buffer power supply|
JTAG Emulation Interface
|Software||D.Module2.BIOS||DSP initialization configuration
programming support for Flash, UART, USB
|Setup Utility||USB- and RS232-based field maintenance tool for program and data uploads, diagnostics|
|Module Config File||ASCII configuration file for application-specific settings|
|TI TCP/IP Software Stack||Available for download from Texas Instruments|
|Power Supply||3.3V||single supply|
|Mechanics||87 x 58 x 33 mm||self-stacking design, board-spacing 10mm
four IEEE-1386 high-density connectors