D.Module2.TS203

ADSP-TS203 Ultra High Performance Floating Point DSP board

The D.Module2.TS203 is designed for high-end signal processing applications like:

  • Wireless communications
  • Medical and industrial image processing
  • Ultrasonic and eddy current material inspection
  • High-end measurement systems
  • Radar and sonar systems
D.Module2.TS203 DSP Board

4000 MMACS DSP and a 500 Mbyte/sec peripheral bus provide adequate bandwidth to interface and process high-speed data converters and co-operate with FPGAs. The modular, self-stacking concept facilitates building complete signal processing systems and allows to insert FPGA boards into the signal processing chain, between the data acquisition front end and the DSP. The D.Module2.TS203 communicates via a high-speed USB2.0 interface and two UARTs with RS232 and RS422 interface. A large in-system user-programmable CPLD accommodates application-specific extensions like PWM outputs, quadrature encoder, Bit-I/O, and serial ports. All on-board peripherals are comfortably initialized and programmed via BIOS functions.

This module is based on the Analog Devices TigerSHARC® ADSP-TS203, an ultra-high performance floating point DSP. Two high-speed link ports with LVDS interface can be used to build a multiprocessor cluster, or as an additional high-speed data path to FPGAs. 8 Mbyte Flash Memory provide sufficient non-volatile storage for application programs and data. Program code and data reside in the 4 MBit TS203 internal memory and in the 64 Mbyte SDRAM, operating at 125 MHz. The external bus interface supports direct (flyby) DMA transfers between synchronous peripherals and SDRAM

A base board D.Module2.Base is available for prototyping and evaluation.

Modular Self Stacking & Extending Functionality

The modular, self-stacking concept facilitates building complete signal processing systems and allows for the addition of FPGA boards into the signal processing chain, between the data acquisition front end and the DSP. All on-board peripherals are comfortably initialized and programmed via D.Module2.BIOS functions.

In situations where additional functionality is required, developers can extend the capabilities of the D.Module2.TS203, using optionally available data acquisition and I/O modules, or with their own application-specific hardware. External hardware is easily interfaced with the ADSP-TS203 processor via its external bus interface

Product Features

DSP ADSP-TS203 500 MHz, 32/40-bit floating-point, 8/16/32/64-bit fixed-point, 3GFLOPS
Memory DSP-internal 
SDRAM 
Flash
512 Kbyte 
64 Mbyte, 125 MHz operation, 32-bit wide 
8 MByte, 8-bit wide, sector architecture
USB 2.0 (480 Mbit/s) 
1.1 (12 Mbit/s)
Philips isp1582, up to 14 endpoints, 8 Kbyte shared FIFO, DMA support
UART 2 16C752, max. 230.4 Kbaud RS232, 3 Mbaud RS422/485,
64 byte transmit and receive FIFOs, DMA support 
hardware and software auto flow-control
RS232 and RS422/485 line interface
External Bus Interface 32-bit data 
20-bit address
supports asynchronous and synchronous transfers
programmable wait states and clock (75/83/100/125 MHz)
up to 500 Mbyte/s transfer rate
Timer 2 32 bit, additional hardware timers can be implemented in the User-CPLD
Link Ports 2 LVDS high-speed links for multiprocessor clusters or additional FPGA interface, total throughput up to 1 Gbyte/s
Serial Ports - SPORTs, I²C, and SPI can be implemented in the User-CPLD
GPIO 20 16 user-programmable I/O pins, 4 GPIO pins from DSP
Miscellaneous jumperless design
Watchdog
JTAG Emulation Interface
Software D.Module2.BIOS initialization and programming algorithms for all on board resources
Setup Utility USB- and RS232-based field maintenance tool for program and data uploads, User-CPLD reprogramming, diagnostics
Module Config File ASCII configuration file for application-specific settings
Power Supply 3.3V single supply
Mechanics 87 x 58 x 15 mm self-stacking design, board-spacing 10mm
four IEEE-1386 high-density connectors
RoHS conformity yes